1.Field of the Invention
The present invention relates to semi-conductor memory. In particular, it relates to read/write circuitry of static and dynamic random access memory (SRAM and DRAM).
2. Background Information
A semi-conductor memory usually includes a number of memory cells (hereinafter simply cells) arranged in a matrix form having rows and columns. Typically, cells of the same row share a common word line, and cells of the same column share a common pair of bit lines (see FIG. 1). In the case of a DRAM device using a folded bit-line structure, cells of the same column are arranged so that the cells are connected alternately to the bit lines. The bit-line pair is in turn connected to a sense amplifier, which is a regenerative latch. The bit-line pair is also connected to a pair of column switches constituted with gates. The gates of the column switches are controlled by a column select signal. Multiple columns are connected together and to a pair of data lines. The data lines in turn are connected to a read data amplifier and a write buffer. The folded bit-line scheme and its variations are well taught in various literature, for examples, "A 55 ns 16Mb DRAM, T. Takeshima et al, Digest of ISSCC, Feb. 1989, pp. 246-247", "A 60 ns 3.3V 16Mb DRAM, K. Arimoto, et al, Digest of ISSCC, Feb. 1989, pp. 244-245", and U.S. Pat. No. 4,980,862, Foss. In case of a SRAM, the bit-line pair is connected to the column switches before being connected to the sense-amplifier. In this way, multiple columns can share a single sense-amplifier. Such scheme is exemplified by the one described in U.S. Pat. No. 5,357,479, "Static Random Access Memory Capable of Preventing Erroneous Writing, M. Matsui".
In case of a divided bit line architecture, such as the one described in "A 1Mbit CMOS Dynamic RAM with a Divided Bitline Matix Architecture, R. T. Taylor et al, IEEE JSSCC, vol sc-20, no. 5 Oct. 1985, pp. 894-902", the cells are connected to segment-lines. Multiple pairs of segment lines in turn are connected to a pair of bit lines through segment switches. In these schemes, the bit-line pair and data-line pair carry complementary signals during read or write operations to increase the signal-to-noise ratio. The data lines form the communication links between the cell array and the I/O circuits of the DRAM. In other schemes, multiple memory arrays are connected in parallel to the data lines, and the data lines form a data bus connecting the cell arrays to the I/O circuits of the memory device.
The bit lines, in general, have relatively large capacitive loading because of cell multiplexing. To conserve die area, a bi-stable sense-amplifier consists of a cross-coupled pair of PMOS transistors and a cross-coupled pair of NMOS transistors are usually employed. The sources of the NMOS cross-coupled pair are connected to the drain of yet another NMOS transistor with its source coupled to ground. The gate of this other NMOS transistor is controlled by a N_Sense_Enable signal. Similarly, the sources of the PMOS cross-coupled pair are connected to the drain of yet another PMOS transistor with its source coupled to VGC. The gate of this other PMOS transistor is controlled by a P_sense_Enable signal. The P_Sense_Enable and N_Sense_Enable signals are used to control the turn-on of the sense amplifier. The bit lines are both input and output signals of the sense-amplifier.
In the case of DRAM, the regenerative sense-amplifier accomplishes data restoration as well as signal amplification. Due to the relatively weak cell signal, the small device size of the amplifier limited by the small area in the tight-pitch column area, and the large bit line capacitance, bit-line sensing is relatively slow. Another reason for the slow sensing is because of the large number of sense-amplifiers getting turned on simultaneously during bit-line sensing. This causes large amount of current flow through the on-chip power lines to the sense-amplifiers, creating large power spikes that can degrade the signal-to-noise ratio during the sensing operation. In order to reduce the power spike, sense amplifiers with multi-step turn on is used to limit the peak current going through the sense amplifiers. An example of multi-step sensing is described in U.S. Pat. No. 4,370,575 "High Performance Dynamic Sense Amplifier with Active Loads", McAlexander, III et al. In a multi-step sensing scheme, the sense-amp turn-on transistors are divided into multiple transistors with their gates controlled by signals which are activated one after the other, so as to limit the peak current during sense-amp turn on. However, the multi-stage turn on lengthens the sensing time and thus the read and write time.
The data lines also have large capacitive loading due to the column multiplexing and, in some cases, array multiplexing. Data line signal rise and fall time is relatively long. In the cases where a static comparator is used for data amplification, such as the one described in "A 1-Mbit CMOS Dynamic RAM with a Divided Bitline Matrix Architecture, R. T. Taylor at al, IEEE JSSC, vol. sc-20, no. 5, pp 894-902, Oct. 1985", the data-line pairs are pulled high by a pair of PMOS devices. During operation, the sense-amplifier is turned on so that signal development in the bit-lines are well established before the column switches are turned on. This requires the sense-amplifier to be turned on much earlier than the column switches so that voltage differential on the outputs of the sense-amplifier is big enough to withstand the disturbance caused by the turn-on of the column switches. In a prior art scheme described in "A 20-ns 128-kbit.times.4 High-Speed DRAM with 330-Mbit/s Data Rate, N. C. C. Lu at el, IEEE JSSC, vol. 23 no. 5, Oct 1988, pp. 1140-1148", a two-stage regenerative data-amplifier (I/O sensing amplifier) is used to amplify signals from the column switches during data read operations to speed up the data restore operation in the sense-amplifier. [The reference was silent with respect to usage of data-amplifier for data write operations.]
Furthermore, traditional write driver circuit is separated from the data amplifier circuit so as to simplify the control during write operations. Due to the relatively large capacitance in the data lines, the write driver takes up relatively large area. The area is not a significant problem for memory devices with few data lines. However, for a memory device that requires wide write bandwidth with many bits of data being written simultaneously to the cell array, the amount of die area consumed by the write driver has become a significant issue. This is especially true for the new generation of memory devices where it will not be uncommon to write a hundred or more bits of data to the cell array at the same time.
Thus, a faster operating read-write circuitry, without the disadvantages of the prior art, for memory devices with a relatively wide write bandwidth, is desired.